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1/22 july 2000 m29f800at m29f800ab 8 mbit (1mb x8 or 512kb x16, boot block) single supply flash memory n single 5v 10% supply voltage for program, erase and read operations n access time: 70ns n programming time 8 m s per byte/word typical n 19 memory blocks 1 boot block (top or bottom location) 2 parameter and 16 main blocks n program/erase controller embedded byte/word program algorithm embedded multi-block/chip erase algorithm status register polling and toggle bits ready/busy output pin n erase suspend and resume modes read and program another block during erase suspend n temporary block unprotection mode n low power consumption standby and automatic standby n 100,000 program/erase cycles per block n 20 years data retention defectivity below 1 ppm/year n electronic signature manufacturer code: 0020h top device code m29f800at: 00ech bottom device code m29f800ab: 0058h 44 1 tsop48 (n) 12 x 20mm so44 (m) figure 1. logic diagram ai02198b 19 a0-a18 w dq0-dq14 v cc m29f800at m29f800ab e v ss 15 g rp dq15a1 byte rb
m29f800at, m29f800ab 2/22 figure 2. tsop connections dq3 dq9 dq2 dq0 dq6 dq13 dq14 dq12 dq10 dq15a1 v cc dq4 dq5 dq7 ai02199 m29f800at m29f800ab 12 1 13 24 25 36 37 48 dq8 dq1 dq11 a16 byte v ss a0 v ss a6 a3 a8 a9 a17 a10 a2 a7 nc nc nc nc a1 a18 a4 a5 a12 a13 a11 a15 a14 rp w rb g e table 1. signal names a0-a18 address inputs dq0-dq7 data inputs/outputs dq8-dq14 data inputs/outputs dq15a1 data input/output or address input e chip enable g output enable w write enable rp reset/block temporary unprotect rb ready/busy output byte byte/word organization select v cc supply voltage v ss ground nc not connected internally summary description the m29f800a is an 8 mbit (1mb x8 or 512kb x16) non-volatile memory that can be read, erased and reprogrammed. these operations can be per- formed using a single 5v supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. each block can be protected independently to prevent accidental program or erase commands from modifying the memory. program and erase commands are writ- ten to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. figure 3. so connections g dq0 dq8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 dq7 a12 a16 byte dq15a1 dq5 dq2 dq3 v cc dq11 dq4 dq14 a9 w rb a4 a18 rp a7 ai02101b m29f800at m29f800ab 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 dq1 dq9 a6 a5 dq6 dq13 44 39 38 37 36 35 34 33 a11 a10 dq10 21 dq12 40 43 1 42 41 a17 a8
3/22 m29f800at, m29f800ab the blocks in the memory are asymmetrically ar- ranged, see tables 3 and 4, block addresses. the first or last 64 kbytes have been divided into four additional blocks. the 16 kbyte boot block can be used for small initialization code to start the micro- processor, the two 8 kbyte parameter blocks can be used for parameter storage and the remaining 32k is a small main block where the application may be stored. chip enable, output enable and write enable sig- nals control the bus operation of the memory. they allow simple connection to most micropro- cessors, often without additional logic. the memory is offered in tsop48 (12 x 20mm) and so44 packages and it is supplied with all the bits erased (set to '1'). table 2. absolute maximum ratings (1) note: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum voltage may undershoot to 2v during transition and for less than 20ns during transitions. symbol parameter value unit t a ambient operating temperature (temperature range option 1) 0 to 70 c ambient operating temperature (temperature range option 6) 40 to 85 c ambient operating temperature (temperature range option 3) 40 to 125 c t bias temperature under bias 50 to 125 c t stg storage temperature 65 to 150 c v io (2) input or output voltage 0.6 to 6 v v cc supply voltage 0.6 to 6 v v id identification voltage 0.6 to 13.5 v
m29f800at, m29f800ab 4/22 table 3. top boot block addresses, m29f800at # size (kbytes) address range (x8) address range (x16) 18 16 fc000h-fffffh 7e000h-7ffffh 17 8 fa000h-fbfffh 7d000h-7dfffh 16 8 f8000h-f9fffh 7c000h-7cfffh 15 32 f0000h-f7fffh 78000h-7bfffh 14 64 e0000h-effffh 70000h-77fffh 13 64 d0000h-dffffh 68000h-6ffffh 12 64 c0000h-cffffh 60000h-67fffh 11 64 b0000h-bffffh 58000h-5ffffh 10 64 a0000h-affffh 50000h-57fffh 9 64 90000h-9ffffh 48000h-4ffffh 8 64 80000h-8ffffh 40000h-47fffh 7 64 70000h-7ffffh 38000h-3ffffh 6 64 60000h-6ffffh 30000h-37fffh 5 64 50000h-5ffffh 28000h-2ffffh 4 64 40000h-4ffffh 20000h-27fffh 3 64 30000h-3ffffh 18000h-1ffffh 2 64 20000h-2ffffh 10000h-17fffh 1 64 10000h-1ffffh 08000h-0ffffh 0 64 00000h-0ffffh 00000h-07fffh table 4. bottom boot block addresses, m29f800ab # size (kbytes) address range (x8) address range (x16) 18 64 f0000h-fffffh 78000h-7ffff h 17 64 e0000h-effffh 70000h-77fffh 16 64 d0000h-dffffh 68000h-6ffff h 15 64 c0000h-cffffh 60000h-67fffh 14 64 b0000h-bffffh 58000h-5ffff h 13 64 a0000h-affffh 50000h-57fffh 12 64 90000h-9ffffh 48000h-4ffff h 11 64 80000h-8ffffh 40000h-47fffh 10 64 70000h-7ffffh 38000h-3ffff h 9 64 60000h-6ffffh 30000h-37fffh 8 64 50000h-5ffffh 28000h-2ffff h 7 64 40000h-4ffffh 20000h-27fffh 6 64 30000h-3ffffh 18000h-1ffff h 5 64 20000h-2ffffh 10000h-17fffh 4 64 10000h-1ffffh 08000h-0ffff h 3 32 08000h-0ffffh 04000h-07fffh 2 8 06000h-07fffh 03000h-03fffh 1 8 04000h-05fffh 02000h-02fffh 0 16 00000h-03fffh 00000h-01fffh
5/22 m29f800at, m29f800ab signal descriptions see figure 1, logic diagram, and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a18). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the internal state machine. data inputs/outputs (dq0-dq7). the data in- puts/outputs output the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the internal state machine. data inputs/outputs (dq8-dq14). the data in- puts/outputs output the data stored at the selected address during a bus read operation when byte is high, v ih . when byte is low, v il , these pins are not used and are high impedance. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. data input/output or address input (dq15a-1). when byte is high, v ih , this pin behaves as a data input/output pin (as dq8-dq14). when byte is low, v il , this pin behaves as an address pin; dq15a1 low will select the lsb of the word on the other addresses, dq15a1 high will select the msb. throughout the text consider references to the data input/output to include this pin when byte is high and references to the address in- puts to include this pin when byte is low except when stated explicitly otherwise. chip enable (e). the chip enable, e, activates the memory, allowing bus read and bus write op- erations to be performed. when chip enable is high, v ih , all other pins are ignored. output enable (g). the output enable, g, con- trols the bus read operation of the memory. write enable (w). the write enable, w, controls the bus write operation of the memory's com- mand interface. reset/block temporary unprotect (rp). the re- set/block temporary unprotect pin can be used to apply a hardware reset to the memory or to tem- porarily unprotect all blocks that have been pro- tected. a hardware reset is achieved by holding reset/ block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see the ready/busy output section, table 17 and figure 11, reset/ temporary unprotect ac characteristics for more details. holding rp at v id will temporarily unprotect the protected blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . ready/busy output (rb). the ready/busy pin is an open-drain output that can be used to identify when the memory array can be read. ready/busy is high-impedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy be- comes high-impedance. see table 17 and figure 11, reset/temporary unprotect ac characteris- tics. during program or erase operations ready/busy is low, v ol . ready/busy will remain low during read/reset commands or hardware resets until the memory is ready to enter read mode. the use of an open-drain output allows the ready/ busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. byte/word organization select (byte). the byte/ word organization select pin is used to switch be- tween the 8-bit and 16-bit bus modes of the mem- ory. when byte/word organization select is low, v il , the memory is in 8-bit mode, when it is high, v ih , the memory is in 16-bit mode. v cc supply voltage. the v cc supply voltage supplies the power for all operations (read, pro- gram, erase etc.). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from ac- cidentally damaging the data during power up, power down and power surges. if the program/ erase controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. a 0.1 m f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc4 . v ss ground. the v ss ground is the reference for all voltage measurements.
m29f800at, m29f800ab 6/22 table 5. bus operations, byte = v il note: x = v il or v ih . table 6. bus operations, byte = v ih note: x = v il or v ih . operation e g w address inputs dq15a1, a0-a18 data inputs/outpu ts dq14-dq8 dq7-dq0 bus read v il v il v ih cell address hi-z data output bus write v il v ih v il command address hi-z data input output disable x v ih v ih x hi-z hi-z standby v ih x x x hi-z hi-z read manufacturer code v il v il v ih a0 = v il ,a1=v il ,a9=v id , others v il or v ih hi-z 20h read device code v il v il v ih a0 = v ih ,a1=v il ,a9=v id , others v il or v ih hi-z ech (m29f800at) 58h (m29f800ab) operation e g w address inputs a0-a18 data inputs/outpu ts dq15a1, dq14-dq0 bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih x hi-z standby v ih x x x hi-z read manufacturer code v il v il v ih a0 = v il ,a1=v il ,a9=v id , others v il or v ih 0020h read device code v il v il v ih a0 = v ih ,a1=v il ,a9=v id , others v il or v ih 00ech (m29f800at) 0058h (m29f800ab) bus operations there are five standard bus operations that control the device. these are bus read, bus write, out- put disable, standby and automatic standby. see tables 5 and 6, bus operations, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. bus read. bus read operations read from the memory cells, or specific registers in the com- mand interface. a valid bus read operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 8, read mode ac waveforms, and table 14, read ac characteristics, for details of when the output becomes valid. bus write. bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the ad- dress inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the com- mand interface on the rising edge of chip enable or write enable, whichever occurs first. output en- able must remain high, v ih , during the whole bus write operation. see figures 9 and 10, write ac waveforms, and tables 15 and 16, write ac characteristics, for details of the timing require- ments. output disable. the data inputs/outputs are in the high impedance state when output enable is high, v ih . standby. when chip enable is high, v ih , the data inputs/outputs pins are placed in the high- impedance state and the supply current is re- duced to the standby level. when chip enable is at v ih the supply current is reduced to the ttl standby supply current, i cc2 . to further reduce the supply current to the cmos standby supply current, i cc3 , chip enable should be held within v cc 0.2v. for standby current levels see table 13, dc characteristics.
7/22 m29f800at, m29f800ab during program or erase operations the memory will continue to use the program/erase supply current, i cc4 , for program or erase operations un- til the operation completes. automatic standby. if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 150ns or more the memory enters automatic standby where the internal supply current is re- duced to the cmos standby supply current, i cc3 . the data inputs/outputs will still output data if a bus read operation is in progress. special bus operations additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. these bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. they require v id to be applied to some pins. electronic signature. the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in tables 5 and 6, bus operations. block protection and blocks unprotection. each block can be separately protected against acci- dental program or erase. protected blocks can be unprotected to allow data to be changed. block protection and block unprotection operations must only be performed on programming equip- ment. for further information refer to application note an1122, applying protection and unprotection to m29 series flash. command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. failure to observe a valid sequence of bus write operations will result in the memory return- ing to read mode. in this case, after at least 50ns, an address transition or chip enable going low is required before reading correct data. the long command sequences are imposed to maximize data security. the address used for the commands changes de- pending on whether the memory is in 16-bit or 8- bit mode. see either table 7, or 8, depending on the configuration that is being used, for a summary of the commands. read/reset command. the read/reset com- mand returns the memory to its read mode where it behaves like a rom or eprom. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. if the read/reset command is issued during a block erase operation or following a programming or erase error then the memory will take up to 10 m s to abort. during the abort period no valid data can be read from the memory. issuing a read/reset command during a block erase operation will leave invalid data in the memory. auto select command. the auto select com- mand is used to read the manufacturer code, the device code and the block protection status. three consecutive bus write operations are re- quired to issue the auto select command. once the auto select command is issued the memory remains in auto select mode until another com- mand is issued. from the auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the manufacturer code for stmicroelectronics is 0020h. the device code can be read using a bus read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . the device code for the m29f800at is 00ech and for the m29f800ab is 0058h. the block protection status of each block can be read using a bus read operation with a0 = v il , a1 = v ih , and a12-a18 specifying the address of the block. the other address bits may be set to ei- ther v il or v ih . if the addressed block is protected then 01h is output on data inputs/outputs dq0- dq7, otherwise 00h is output. program command. the program command can be used to program a value to one address in the memory array at a time. the command re- quires four bus write operations, the final write op- eration latches the address and data in the internal state machine and starts the program/erase con- troller. if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given. during the program operation the memory will ig- nore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in table 9. bus read op- erations during the program operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode.
m29f800at, m29f800ab 8/22 table 7. commands, 16-bit mode, byte = v ih table 8. commands, 8-bit mode, byte = v il note: x don't care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal. the command interface only uses a1, a0-a10 and dq0-dq7 to verify the commands; a11-a18, dq8-dq14 and dq15 are don't care. dq15a1 is a1 when byte is v il or dq15 when byte is v ih . read/reset. after a read/reset command, read the memory as normal until another command is issued. auto select. after an auto select command, read manufacturer id, device id or block protection status. program, chip erase, block erase. after these commands read the status register until the program/erase controller completes and the memory returns to read mode. add additional blocks during block erase command with additional bus writ e operations until the timeout bit is set. erase suspend. after the erase suspend command read non-erasing memory blocks as normal, issue auto select and program commands on non-erasing blocks as normal. erase resume. after the erase resume command the suspended erase operation resumes, read the status register until the program/ erase controller completes and the memory returns to read mode. command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 aaa aa 555 55 x f0 auto select 3 aaa aa 555 55 aaa 90 program 4 aaa aa 555 55 aaa a0 pa pd chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase 6+ aaa aa 555 55 aaa 80 aaa aa 555 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 note that the program command cannot change a bit set at '0' back to '1'. one of the erase com- mands must be used to set all the bits in a block or in the whole memory from '0' to '1'. chip erase command. the chip erase com- mand can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation ap- pears to start but will terminate within about 100 m s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands. it is not possible to issue any com- mand to abort the operation. typical chip erase times are given in table 9. all bus read opera- tions during the chip erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the
9/22 m29f800at, m29f800ab memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the chip erase command sets all of the bits in un- protected blocks of the memory to '1'. all previous data is lost. block erase command. the block erase com- mand can be used to erase a list of one or more blocks. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller about 50 m s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each additional block must therefore be selected within 50 m s of the last block. the 50 m s timer restarts when an additional block is selected. the status register can be read after the sixth bus write operation. see the status register for details on how to identify if the program/erase controller has started the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100 m s, leaving the data un- changed. no error condition is given when protect- ed blocks are ignored. during the block erase operation the memory will ignore all commands except the erase suspend and read/reset commands. typical block erase times are given in table 9. all bus read opera- tions during the block erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to '1'. all previous data in the selected blocks is lost. erase suspend command. the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus write operation. the program/erase controller will suspend within 15 m s of the erase suspend command being is- sued. once the program/erase controller has stopped the memory will be set to read mode and the erase will be suspended. if the erase suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start im- mediately when the erase resume command is issued. it will not be possible to select any further blocks for erasure after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. reading from blocks that are being erased will output the status register. it is also possible to enter the auto select mode: the memory will behave as in the auto select mode on all blocks until a read/reset command returns the memory to erase suspend mode. erase resume command. the erase resume command must be used to restart the program/ erase controller from erase suspend. an erase can be suspended and resumed more than once. table 9. program, erase times and program, erase endurance cycles (t a = 0 to 70 c, 40 to 85 c or 40 to 125 c) note: 1. t a =25 c, v cc =5v. parameter min typ (1) typical after 100k w/e cycles (1) max unit chip erase (all bits in the memory set to `0') 3 3 sec chip erase 8 8 30 sec block erase (64 kbytes) 0.6 0.6 4 sec program (byte or word) 8 8 150 m s chip program (byte by byte) 9 9 35 sec chip program (word by word) 4.5 4.5 18 sec program/erase cycles (per block) 100,000 cycles
m29f800at, m29f800ab 10/22 status register bus read operations from any address always read the status register during program and erase operations. it is also read during erase sus- pend when an address within a block being erased is accessed. the bits in the status register are summarized in table 10, status register bits. data polling bit (dq7). the data polling bit can be used to identify whether the program/erase controller has successfully completed its opera- tion or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being pro- grammed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the ad- dress just programmed output dq7, not its com- plement. during erase operations the data polling bit out- puts '0', the complement of the erased state of dq7. after successful completion of the erase op- eration the memory returns to read mode. in erase suspend mode the data polling bit will output a '1' during a bus read operation within a block being erased. the data polling bit will change from a '0' to a '1' when the program/erase controller has suspended the erase operation. figure 4, data polling flowchart, gives an exam- ple of how to use the data polling bit. a valid ad- dress is the address being programmed or an address within the block being erased. toggle bit (dq6). the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has re- sponded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from '0' to '1' to '0', etc., with succes- sive bus read operations at any address. after successful completion of the operation the memo- ry returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. figure 5, data toggle flowchart, gives an exam- ple of how to use the data toggle bit. error bit (dq5). the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to '1' when a pro- gram, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set at '0' back to '1' and attempting to do so may or may not set dq5 at `1'. in both cases, a succes- sive bus read operation will show the bit is still `0'. one of the erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. table 10. status register bits note: unspecified data bits should be ignored. operation address dq7 dq6 dq5 dq3 dq2 rb program any address dq7 toggle 0 0 program during erase suspend any address dq7 toggle 0 0 program error any address dq7 toggle 1 0 chip erase any address 0 toggle 0 1 toggle 0 block erase before timeout erasing block 0 toggle 0 0 toggle 0 non-erasing block 0 toggle 0 0 no toggle 0 block erase erasing block 0 toggle 0 1 toggle 0 non-erasing block 0 toggle 0 1 no toggle 0 erase suspend erasing block 1 no toggle 0 toggle 1 non-erasing block data read as normal 1 erase error good block address 0 toggle 1 1 no toggle 0 faulty block address 0 toggle 1 1 toggle 0
11/22 m29f800at, m29f800ab figure 4. data polling flowchart read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai03598 dq7 = data yes no yes no dq5 =1 dq7 = data yes no figure 5. data toggle flowchart read dq6 start read dq6 twice fail pass ai01370b dq6 = toggle no no yes yes dq5 =1 no yes dq6 = toggle read dq5 & dq6 erase timer bit (dq3). the erase timer bit can be used to identify the start of program/erase controller operation during a block erase com- mand. once the program/erase controller starts erasing the erase timer bit is set to '1'. before the program/erase controller starts the erase timer bit is set to '0' and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. alternative toggle bit (dq2). the alternative toggle bit can be used to monitor the program/ erase controller during erase operations. the al- ternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from '0' to '1' to '0', etc., with successive bus read operations from addresses within the blocks being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from '0' to '1' to '0', etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to ad- dresses within blocks not being erased will output the memory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the er- ror. the alternative toggle bit changes from '0' to '1' to '0', etc. with successive bus read opera- tions from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased cor- rectly.
m29f800at, m29f800ab 12/22 figure 6. ac testing input output waveform ai01275b 3v high speed 0v 1.5v 2.4v standard 0.45v 2.0v 0.8v figure 7. ac testing load circuit ai03027 1.3v out c l = 30pf or 100pf c l includes jig capacitance 3.3k w 1n914 device under test table 12. capacitance (t a =25 c, f = 1 mhz) note: sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in =0v 6pf c out output capacitance v out =0v 12 pf table 11. ac measurement conditions parameter m29f800a 70 90 ac test conditions high speed standard load capacitance (c l ) 30pf 100pf input rise and fall times 10ns 10ns input pulse voltages 0 to 3v 0.45 to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2.0v
13/22 m29f800at, m29f800ab table 13. dc characteristics (t a = 0 to 70 c, 40 to 85 c or 40 to 125 c) note: 1. sampled only, not 100% tested. 2. t a =25 c, v cc =5v. symbol parameter test condition min typ. (2) max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 1 m a i cc1 supply current (read) e=v il ,g=v ih , f = 6mhz 10 20 ma i cc2 supply current (standby) ttl e=v ih 1ma i cc3 supply current (standby) cmos e=v cc 0.2v, rp = v cc 0.2v 35 150 m a i cc4 (1) supply current (program/erase) program/erase controller active 20 ma v il input low voltage 0.5 0.8 v v ih input high voltage 2 v cc +0.5 v v ol output low voltage i ol = 5.8ma 0.45 v v oh output high voltage ttl i oh = 2.5ma 2.4 v output high voltage cmos i oh = 100 m av cc 0.4 v v id identification voltage 11.5 12.5 v i id identification current a9 = v id 100 m a v lko (1) program/erase lockout supply voltage 3.2 4.2 v
m29f800at, m29f800ab 14/22 figure 8. read mode ac waveforms ai02981 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a18/ a1 g dq0-dq7/ dq8-dq15 e telqv tehqx tghqz valid tbhqv telbl/telbh tblqz byte table 14. read ac characteristics (ta = 0 to 70 c, 40 to 85 c or 40 to 125 c) note: 1. sampled only, not 100% tested. symbol alt parameter test condition m29f800a unit 70 90 t avav t rc address valid to next address valid e=v il , g=v il min 70 90 ns t avqv t acc address valid to output valid e=v il , g=v il max 70 90 ns t elqx (1) t lz chip enable low to output transition g = v il min 0 0 ns t elqv t ce chip enable low to output valid g=v il max 70 90 ns t glqx (1) t olz output enable low to output transition e=v il min 0 0 ns t glqv t oe output enable low to output valid e=v il max 30 35 ns t ehqz (1) t hz chip enable high to output hi-z g=v il max 20 20 ns t ghqz (1) t df output enable high to output hi-z e = v il max 20 20 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 ns t elbl t elbh t elfl t elfh chip enable to byte low or high max 5 5 ns t blqz t flqz byte low to output hi-z max 20 20 ns t bhqv t fhqv byte high to output valid max 30 40 ns
15/22 m29f800at, m29f800ab figure 9. write ac waveforms, write enable controlled ai02183 e g w a0-a18/ a1 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl table 15. write ac characteristics, write enable controlled (t a = 0 to 70 c, 40 to 85 c or 40 to 125 c) note: 1. sampled only, not 100% tested. symbol alt parameter m29f800a unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t elwl t cs chip enable low to write enable low min 0 0 ns t wlwh t wp write enable low to write enable high min 45 45 ns t dvwh t ds input valid to write enable high min 30 45 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whwl t wph write enable high to write enable low min 20 20 ns t avwl t as address valid to write enable low min 0 0 ns t wlax t ah write enable low to address transition min 45 45 ns t ghwl output enable high to write enable low min 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 ns t whrl (1) t busy program/erase valid to rb low max 30 35 ns t vchel t vcs v cc high to chip enable low min 50 50 m s
m29f800at, m29f800ab 16/22 table 16. write ac characteristics, chip enable controlled (t a = 0 to 70 c, 40 to 85 c or 40 to 125 c) note: 1. sampled only, not 100% tested. symbol alt parameter m29f800a unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t wlel t ws write enable low to chip enable low min 0 0 ns t eleh t cp chip enable low to chip enable high min 45 45 ns t dveh t ds input valid to chip enable high min 30 45 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t ehel t cph chip enable high to chip enable low min 20 20 ns t avel t as address valid to chip enable low min 0 0 ns t elax t ah chip enable low to address transition min 45 45 ns t ghel output enable high chip enable low min 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 ns t ehrl (1) t busy program/erase valid to rb low max 30 35 ns t vchwl t vcs v cc high to write enable low min 50 50 m s figure 10. write ac waveforms, chip enable controlled ai02184 e g w a0-a18/ a1 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl
17/22 m29f800at, m29f800ab table 17. reset/block temporary unprotect ac characteristics (t a = 0 to 70 c, 40 to 85 c or 40 to 125 c) note: 1. sampled only, not 100% tested. symbol alt parameter m29f800a unit 70 90 t phwl (1) t phel t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 50 ns t rhwl (1) t rhel (1) t rhgl (1) t rb rb high to write enable low, chip enable low, output enable low min 0 0 ns t plpx t rp rp pulse width min 500 500 ns t plyh (1) t ready rp low to read mode max 10 10 m s t phphh (1) t vidr rp rise time to v id min 500 500 ns figure 11. reset/block temporary unprotect ac waveforms ai02931 rb w, rp tplpx tphwl, tphel, tphgl tplyh tphphh e, g trhwl, trhel, trhgl
m29f800at, m29f800ab 18/22 table 18. ordering information scheme note: the last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content bits erased to `1'. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: m29f800ab 70 n 1 t device type m29 operating voltage f=v cc =5v 10% device function 800a = 8mbit (1mb x8 or 512kb x16), boot block array matrix t = top boot b = bottom boot speed 70 = 70 ns 90 = 90 ns package n = tsop48: 12 x 20 mm m = so44 temperature range 1=0to70 c 3 = 40 to 125 c 6=40to85 c optio n t = tape & reel packing
19/22 m29f800at, m29f800ab table 19. revision history date revision details july 1999 first issue 09/21/99 removed 55ns speed option i cc1 and i cc3 typ. specification added (table 13) typ. specification added (table 13) 10/04/99 i cc3 test condition change (table 13) 11/12/99 block protection and unprotection paragraph changed 01/14/00 command interface paragraph changed 07/28/00 new document template document type: from preliminary data to data sheet status register bit dq5 clarification data polling flowchart diagram change (figure 4) data toggle flowchart diagram change (figure 5)
m29f800at, m29f800ab 20/22 table 20. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 11.90 12.10 0.4685 0.4764 e 0.50 0.0197 l 0.50 0.70 0.0197 0.0279 a 0 5 0 5 n48 48 cp 0.10 0.0039 figure 12. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline drawing is not to scale. tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a
21/22 m29f800at, m29f800ab table 21. so44 - 44 lead plastic small outline, 525 mils body width, package mechanical data symbol mm inches typ min max typ min max a 2.42 2.62 0.0953 0.1031 a1 0.22 0.23 0.0087 0.0091 a2 2.25 2.35 0.0886 0.0925 b 0.50 0.0197 c 0.10 0.25 0.0039 0.0098 d 28.10 28.30 1.1063 1.1142 e 13.20 13.40 0.5197 0.5276 e 1.27 0.0500 h 15.90 16.10 0.6260 0.6339 l 0.80 0.0315 a 3 3 n44 44 cp 0.10 0.0039 figure 13. so44 - 44 lead plastic small outline, 525 mils body width, package outline drawing is not to scale. so-b e n cp b e a2 d c l a1 a h a 1
m29f800at, m29f800ab 22/22 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a . http://w ww.st.com

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